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1 kv rms quad - channel dig ital isolators adum7440/adum7441/adum7442 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted b y implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 C 2011 analog devices, inc. all rights reserved. features small, 16 - lead qsop 1000 v rms isolation rating safety an d regulatory approvals ul recognition ul 1577 : 1000 v rms for 1 minute csa component acceptance notice #5a (pending) low power operation 5 v operation 2.25 ma per channel maximum @ 0 mbp s to 1 mbps 11.5 ma per channel maximum @ 25 mbps 3.3 v operation 1.5 ma per channel maximum @ 0 mbps to 1 mbps 8.25 ma per channel maximum @ 25 mbps bidirectional communication up to 25 mbps data rate (nrz) 3 v/5 v level translation high temperature oper ation: 105c high common - mode transient immunity: >15 kv/ s applications general - purpose, multichannel isolation spi interface/data converter isolation rs - 232/rs - 422/rs - 485 transceivers industrial field bus isolation general description the adum744x 1 are 4 - channel digital isolators based on the analog devices, inc., i coupler? technology. combining high speed cmos and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to the alte rnatives, such as optocoupler devices and other integrated couplers. the adum744x family of quad 1 kv digital isolation devices is packaged in a small 16 - lead qsop. while most 4 - channel isolators come in 16 - lead wide soic packages, the adum744x frees almo st 70% of board space and yet can still withstand high isolation voltage and meet regulatory requirements such as ul and csa standards (pending). in addition to the space savings, the adum744x offers a lower price than 2.5 kv or 5 kv isolators where only f unctional isolation is needed. this family, like many analog devices isolators, offers very low power consumption, consuming one - tenth to one - sixth the power of comparable isolators at comparable data rates up to 25 mbps. despite the low power consumpti on, all models of the adum744x provide low pulse width distortion (< 5 ns for c grade). in addition, every model has an input glitch filter to protect against extraneous noise disturbances. the adum744x isolators provide four independent isolation chann els in a variety of channel configurations and two data rates (see the ordering guide ) up to 25 mbps. all models operate with the supply voltage on either side ranging from 3.0 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. all products also have an output default high logic state in the absence of the input power. 1 protected by u.s. patents 5,952,849, 6,873,065 an d 7,075,329. other patents pending. functional block dia grams encode decode encode decode encode decode encode decode v dd1a gnd 1 v ia v ib v ic v id v dd1b gnd 1 v dd2a gnd 2 v oa v ob v oc v od v dd2b gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 adum7440 08340-001 figure 1 . adum7440 decode encode encode decode encode decode encode decode v dd1a gnd 1 v ia v ib v ic v od v dd1b gnd 1 v dd2a gnd 2 v oa v ob v oc v id v dd2b gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 adum7441 08340-002 figure 2 . adum7441 decode encode decode encode encode decode encode decode v dd1a gnd 1 v ia v ib v oc v od v dd1b gnd 1 v dd2a gnd 2 v oa v ob v ic v id v dd2b gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 adum7442 08340-003 figure 3 . adum7442
adum7440/adum7441/adum7442 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 v operation ................................ 3 electrical characteristics 3.3 v operation ............................ 4 electrical characteristics mi xed 5 v/3.3 v operation ........ 5 electrical characteristics mixed 3.3 v/5 v operation ........ 6 package characteristics ............................................................... 7 regulatory information ............................................................... 7 insulation and safety - related specifications ............................ 7 recommended o perating conditions .......................................7 absolute maximum ratings ............................................................8 esd caution ...................................................................................8 p in configurations and function descriptions ............................9 typical performance characteristics ........................................... 12 applications information .............................................................. 14 pc board layout ........................................................................ 14 propagation delay - related parameters ................................... 14 dc correctness and m agnetic field immunity ........................... 14 power consumption .................................................................. 15 insulation lifetime ..................................................................... 15 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 2 /1 1 rev. a to rev. b changes to figure 7 ........................................................................ 11 8/1 0 rev. 0 to rev. a change features ................................................................................ 1 changes to table 1 ............................................................................ 3 a dded note 1 , table 1 ...................................................................... 3 changes to table 4 ............................................................................ 4 a dded note 1 , table 4 ...................................................................... 4 changes to tab le 7 ............................................................................ 5 added note 1 , table 7 ...................................................................... 5 changes to table 10 .......................................................................... 6 a dded note 1 , table 10 .................................................................... 6 changes to table 14 .......................................................................... 7 10/09 revision 0: initial version
adum7440/adum7441/adum7442 rev. b | page 3 of 20 specifications elect rical characteristic s 5 v operation all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. minimum/maximum specifications apply over the entire recommended operation range of 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v, and ?40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf, and cmos signal levels, unless otherwise noted. table 1 . a grade c grade parameter s ymbol min typ max min typ max unit test conditions switching specifications data rate 1 25 mbps within pwd limit propagation delay t phl , t plh 50 75 2 9 40 50 ns 50% input to 50% output pulse width distortion pwd 10 25 2 5 ns |t plh ? t ph l | change vs. temperature 5 3 ps/c pulse width pw 250 40 ns within pwd limit propagation delay skew 1 t psk 20 10 ns channel matching codirectional t pskcd 25 2 4 ns opposing - direction t pskod 30 3 6 ns jitter 2 2 ns 1 t psk is the magnitude of the worst - case differenc e in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. table 2 . 1 mbps a grade 25 mbps c grade parameter symbol min typ max min typ max unit test conditions supply current adum7440 i dd1 4.3 5.4 28 35 ma i dd2 2.5 3.6 6.0 11 ma adum7441 i dd1 4.1 4.9 18 26 ma i dd2 3.6 4.7 8.5 14 ma adum7442 i dd1 3.2 4.0 15 20 ma i dd2 3.2 4.0 12 17 ma table 3 . for all models parameter symbol min typ max unit test conditions dc specifications logic high input threshold v ih 0.7 v ddx v logic low input threshold v il 0.3 v ddx v logic high output voltages v oh v ddx ? 0.1 5.0 v i ox = ?20 a, v ix = v ixh v ddx ? 0.4 4 .8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl input current per channel i i ?10 +0.01 +10 a 0 v v i x v ddx su pply current per channel quiescent input supply current i ddi(q) 0.7 6 0.95 ma quiescent output supply current i ddo(q) 0.5 7 0.73 ma dynamic input supply current i ddi(d) 0.2 6 ma/mbps dynamic output supply current i ddo(d) 0.0 5 ma/mbps ac specifications output rise/fall time t r /t f 2.0 ns 10% to 90% common - mode transient immunity 1 |cm| 1 5 2 5 kv/s v ix = v ddx , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps 1 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
adum7440/adum7441/a dum7442 rev. b | page 4 of 20 electrical character istics 3.3 v operation all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.3 v. minimum/maximum specifications apply over the entire recommended operation range of 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v; and ?40c t a + 105c , unless otherwise noted. switching specif ications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 4 . a grade c grade parameter symbol min typ max min typ max unit test conditions switching specifications data rate 1 25 mbps within pwd limit propagation delay t phl , t plh 6 0 8 5 3 7 51 6 6 ns 50% input to 50% output pulse width distortion pwd 10 25 2 5 ns |t plh ? t phl | change vs. temperature 5 3 ps/c pulse width pw 250 40 ns within pwd limit propagation delay skew 1 t psk 2 0 10 ns channel matching codirectional t pskcd 25 3 5 ns opposing - direction t pskod 30 4 7 ns jitter 2 2 ns 1 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltage s, and output load within the recommended operating conditions. table 5 . 1 mbps a, c grades 25 mbps c grade parameter symbol min typ max min typ max unit test conditions supply current adum7440 i dd1 3.0 3 .8 20 28 ma i dd2 1.8 2. 3 4.0 5 .0 ma adum7441 i dd1 2. 8 3.5 14 2 0 ma i dd2 2.5 3.3 5.5 7.5 ma adum7442 i dd1 2.2 2. 7 1 0 13 ma i dd2 2.2 2. 8 8.4 1 1 ma table 6 . for all models parameter symbol min typ max unit test conditions dc specifications logic high inpu t threshold v ih 0.7 v ddx v logic low input threshold v il 0.3 v ddx v logic high output voltages v oh v ddx ? 0.2 3.3 v i ox = ?20 a, v ix = v ixh v ddx ? 0.4 3.1 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl input current per channel i i ?10 +0.01 +10 a 0 v v i x v ddx supply current per channel quiescent input supply current i ddi(q) 0.50 ma quiescent output supply current i ddo(q) 0. 41 ma dynamic i nput supply current i ddi(d) 0.18 ma/mbps dynamic output supply current i ddo(d) 0.0 2 ma/mbps ac specifications output rise/fall time t r /t f 2.8 ns 10% to 90% common - mode transient immunity 1 |cm| 15 20 kv/s v ix = v ddx , v cm = 1000 v, trans ient magnitude = 800 v refresh rate f r 1.1 mbps 1 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd . the common - mode voltage slew rates apply to both rising and falling common - mode voltag e edges.
adum7440/adum7441/adum7442 rev. b | page 5 of 20 electrical character istics mixed 5 v/3.3 v oper ation all typical specifications are at t a = 25c, v dd1 = 5 v, v dd2 = 3.3 v. minimum/maximum specifications apply over the entire recom - mended operation r ange of 4.5 v v dd1 5.5 v, 3.0 v v dd2 3.6 v; and ?40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 7 . a grade c grade parameter symbol min typ max min typ max unit test conditions switching specifications data rate 1 25 mbps within pwd limit propagation delay t phl t plh 5 5 80 30 42 55 ns 50% input to 50% output pulse width distortion pwd 10 25 2 5 ns | t plh ? t phl | change vs. temperature 5 3 ps/c pulse width pw 250 40 ns within pwd limit propagation delay skew 1 t psk 2 0 10 ns channel matching codirectional t pskcd 25 2 5 ns opposing - direction t pskod 30 3 6 ns jitter 2 2 ns 1 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. table 8 . 1 mbps a, c grades 25 mbps c grade parameter symbol min typ max min typ max unit test conditions supply current adum7440 i dd1 4.4 5 .5 28 3 5 ma i dd2 1. 6 2.1 3.5 4.5 ma adum7441 i dd1 3. 7 5.0 19 27 ma i dd2 2.2 2.8 5 .2 7 .0 ma adum7442 i dd1 3.2 3. 9 1 5 2 0 ma i dd2 2.0 2. 6 7.8 1 2 ma table 9 . for all models parameter symbol min typ max unit test conditions dc specifications logic high input threshold v ih 0.7 v ddx v logic low input threshold v il 0.3 v ddx v logic high output voltages v oh v ddx ? 0.1 v ddx v i ox = ?20 a, v ix = v ixh v ddx ? 0.4 v ddx ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl input current per channel i i ?10 +0.01 +10 a 0 v v i x v ddx supply current per channel quiescent input supply current i ddi(q) 0. 77 ma quiescent output supply current i ddo(q) 0. 40 ma dyn amic input supply current i ddi(d) 0.2 6 ma/mbps dynamic output supply current i ddo(d) 0.0 2 ma/mbps ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm| 15 20 kv/s v ix = v ddx , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps 1 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
adum7440/adum7441/a dum7442 rev. b | page 6 of 20 electrical character istics mixed 3.3 v/5 v oper ation all typical specifications are at t a = 25c, v dd1 = 3.3 v, v dd2 = 5 v. minimum/maximum specifications apply over the entire recom - mended opera tion range of 3.0 v v dd1 3.6 v, 4.5 v v dd2 5.5 v, and ?40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 10. a grade c gr ade parameter symbol min typ max min typ max unit test conditions switching specifications data rate 1 25 mbps within pwd limit propagation delay t phl , t plh 5 5 80 31 46 60 ns 50% input to 50% output pulse width distortion pwd 10 25 2 5 ns |t plh ? t phl | change vs. temperature 5 3 ps/c pulse width pw 250 40 ns within pwd limit propagation delay skew 1 t psk 2 0 1 0 ns channel matching codirectional t pskcd 25 2 5 ns opposing - direction t pskod 30 3 7 ns jitter 2 2 ns 1 t psk is the magnitude of the worst - case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. table 11. 1 mbps a, c grades 25 mbps c grade parameter symbol min typ max min typ max unit test conditions supply current adum7440 i dd1 2. 7 3.3 18 24 ma i dd2 2. 5 3. 3 5.7 8 .0 ma adum7441 i dd 1 2. 5 3.3 1 2 2 0 ma i dd2 3.6 4.6 8.0 1 1 ma adum7442 i dd1 2.0 2.4 8.9 1 3 ma i dd2 3.2 4.0 1 2 15 ma table 12 . for all models parameter symbol min typ max unit test conditions dc specifications logic high inpu t threshold v ih 0.7 v ddx v logic low input threshold v il 0.3 v ddx v logic high output voltages v oh v ddx ? 0.1 v ddx v i ox = ?20 a, v ix = v ixh v ddx ? 0.4 v ddx ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl input current per channel i i ?10 +0.01 +10 a 0 v v i x v ddx supply current per channel quiescent input supply current i ddi(q) 0.50 0.60 ma quiescent output supply current i ddo(q) 0.61 0. 73 ma dynamic input supply current i ddi(d) 0.1 7 ma/mbps dynamic output supply current i ddo(d) 0.0 3 ma/mbps ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm| 15 20 kv/s v ix = v ddx , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps 1 |cm| is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd . the common - mode voltage slew rates apply to both rising and falling common - mode voltage edges.
adum7440/adum7441/adum7442 rev. b | page 7 of 20 package characterist ics table 13. parameter symbol min typ max unit test conditions resistance (input -to - output) 1 r i- o 10 13 ? capacitance (input -to - output) 1 c i- o 2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction - to - ambient thermal resistance ja 76 c/w thermocouple located at center of package underside 1 the device is considered a 2 - terminal device: pin 1 through pin 8 are shorted together and pin 9 through pin 16 are shorted together. 2 input capacitance is from any input data pin t o ground. regul atory information the adum744x is approved by the organizations listed in table 14 . see table 18 and the insulation lifetime secti on for recommended maximum working voltages for specific cross - isolation waveforms and insulation levels. table 14. ul csa (p ending) recognized under ul 1577 component recognition program 1 approved under csa component acceptance notice #5a single protection, 1000 v rms isolation voltage basic insulation per csa 60950 -1 - 03 and iec 60950 - 1, 148 v rms (210 v peak) maximum working voltage file e274400 file 205078 1 in accordance with ul 1577, each adum744x is proof te sted by applying an insulation test voltage 1200 v rms for 1 sec (current leakage detection limit = 5 a). insulation and safet y - related specificatio ns table 15. parameter symbol value unit conditions rated dielectric insulation voltage 1000 v rms 1 - minute duration minimum external air gap (clearance) l(i01) 3.8 mm min measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 2.8 mm min measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 2.6 m min insulation distance through insulation tracking resistance (comparative tracking index ) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 08340-007 figure 4 . thermal derating curve, dependence of safety - limiting values with case temperat ure per din v vde v 0884 - 10 recommended operatin g conditions table 16. parameter symbol min max unit operating temperature t a ?40 +105 c supply voltages 1 v dd1 , v dd2 3.0 5.5 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground. see the dc correctness and magnetic field immunity section for in formation on immunity to external magnetic fields.
adum7440/adum7441/a dum7442 rev. b | page 8 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. table 17. parameter rating storage temperature (t st ) range ?65c to +150 c ambient operating temperature (t a ) ?40c to +105c supply voltages (v dd1 , v dd2 ) ?0.5 v to +7.0 v input voltages (v ia , v ib , v ic , v id ) 1, 2 ?0.5 v to v ddi + 0.5 v output voltages (v oa , v ob , v oc , v od ) 1, 2 ?0.5 v to v ddo + 0.5 v average output current per pin 3 side 1 (i o1 ) ?10 ma to +10 ma side 2 (i o2 ) ?10 ma to +10 ma common - mode transients 3 ?100 kv/ s to +100 kv/ s 1 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pc board layout section. 2 see figure 4 for maximum rated current values for various temperatures. 3 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum ratings may cause latch - up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 18 . maximum continuous working voltage 1 parameter max unit constraint ac voltage, bipolar waveform 420 v peak 50- year minimum lifetime ac voltage, unipolar waveform basic insulation 420 v peak 50- year minimum lifetime dc voltage basic insula tion 420 v peak 50- year minimum lifetime 1 refers to continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. table 19 . truth table (positive logic) v ix input 1 v ddi state 2 v ddo state 3 v ox output 1 description h powered powered h normal operation; data is high. l powered powered l normal operation; data is low. x unpowered powered h input unpowered. outputs are in the default high state. outputs return to input state within 1 s of v ddi power restoration. see the pin function descriptions ( table 20 through table 22) for more details. x powered unpowered z output unpowered. output pins are in high impedance state. outputs return to input state within 1 s of v ddo power restoration. see the pin function descriptions ( table 20 through table 22) for more details. 1 v ix and v ox refer to the in put and output signals of a given channel (a, b, c, or d). 2 v ddi refers to the power supply on the input side of a given channel (a, b, c, or d). 3 v ddo refers to the power supply on the output side of a given channel (a, b, c, or d).
adum7440/adum7441/adum7442 rev. b | page 9 of 20 pin configurations a nd function descript ions v dd1a 1 gnd 1 * 2 v ia 3 v ib 4 v dd2a 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v id 6 v od 11 v dd1b 7 v dd2b 10 gnd 1 * 8 gnd 2 * 9 adum7440 top view (not to scale) * pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 08340-004 figure 5 . adum7440 pin configuration table 20 . adum7440 pin function descriptions pin no. mnemonic description 1 v dd1a supply voltage a for isolator side 1 (3.0 v to 5.5 v). pin 1 must be connected externally to pin 7. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd1a (pin 1) and gnd 1 (pin 2). 2 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v id logic input d. 7 v dd1b supply voltage b for isolator side 1 (3.0 v to 5.5 v). pin 7 must be connected externally to pin 1. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd1b (pin 7) and gnd 1 (pin 8). 8 gnd 1 ground 1. ground ref erence for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 9 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 10 v dd2b supply voltage b for isolator side 2 (3.0 v to 5.5 v). pin 10 must be connected externally to pin 16. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd2b (pin 10) and gnd 2 (pin 9). 11 v od logic output d. 12 v oc logic ou tput c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 16 v dd2a supply voltage a for isolator side 2 (3.0 v to 5.5 v). pin 16 must be connected externally to pin 10. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd2a (pin 16) and gnd 2 (pin 15).
adum7440/adum7441/a dum7442 rev. b | page 10 of 20 v dd1a 1 gnd 1 * 2 v ia 3 v ib 4 v dd2a 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 v od 6 v id 11 v dd1b 7 v dd2b 10 gnd 1 * 8 gnd 2 * 9 adum7441 top view (not to scale) * pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 08340-005 figure 6 . adum7441 pin configuration table 21 . adum7441 pin function descriptions pin no. mnemonic description 1 v dd1a supply voltage a for isolator side 1 (3.0 v to 5.5 v). pin 1 must be connected externally to pin 7. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd1a ( pin 1) and gnd 1 (pin 2). 2 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 v dd1b supply voltage b for isolator side 1 (3.0 v to 5.5 v). pin 7 must be connected externally to pin 1. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd1b (pin 7) and gnd 1 (pin 8). 8 gnd 1 ground 1. ground reference for isolat or side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 9 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 10 v dd2b supply voltage b for isolator side 2 (3.0 v to 5.5 v). pin 10 must be connected externally to pin 16. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd2b (pin 10) and gnd 2 (pin 9). 11 v id logic input d. 12 v oc logic output c. 13 v ob lo gic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 16 v dd2a supply voltage a for isolator side 2 (3.0 v to 5.5 v). pin 16 mu st be connected externally to pin 10. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd2a (pin 16) and gnd 2 (pin 15).
adum7440/adum7441/adum7442 rev. b | page 11 of 20 v dd1a 1 gnd 1 * 2 v ia 3 v ib 4 v dd2a 16 gnd 2 * 15 v oa 14 v ob 13 v oc 5 v ic 12 v od 6 v id 11 v dd1b 7 v dd2b 10 gnd 1 * 8 gnd 2 * 9 adum7442 top view (not to scale) * pin 2 and pin 8 are internally connected. connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected. connecting both to gnd 2 is recommended. 08340-006 figure 7 . adum7442pin configuration table 22 . adum7442 pin function descriptions pin no. mnemonic description 1 v dd1a supply voltage a for isolator side 1 (3.0 v to 5.5 v). pin 1 must be connected externally to pin 7. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd1a (pin 1) and gnd 1 (p in 2). 2 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 v dd1b supply v oltage b for isolator side 1 (3.0 v to 5.5 v). pin 7 must be connected externally to pin 1. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd1b (pin 7) and gnd 1 (pin 8). 8 gnd 1 ground 1. ground reference for isolator side 1. pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. 9 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 10 v dd2b supply voltage b for is olator side 2 (3.0 v to 5.5 v). pin 10 must be connected externally to pin 16. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd2b (pin 10) and gnd 2 (pin 9). 11 v id logic input d. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 16 v dd2a supply voltage a for isolator side 2 (3.0 v to 5.5 v). pin 16 must be connected ex ternally to pin 10. connect a ceramic bypass capacitor of value 0.01 f to 0.1 f between v dd2a (pin 16) and gnd 2 (pin 15).
adum7440/adum7441/a dum7442 rev. b | page 12 of 20 typical performance characteristics 08340-015 0 5 10 15 20 25 30 dat a r a te (mbps) 3v 5v 10 8 6 4 2 0 current (ma) figure 8 . typical supply current per input channel vs. data rate for 5 v and 3 v operation 08340-016 current (ma) 0 1 2 3 4 0 5 10 15 20 25 30 dat a r a te (mbps) 5v 3v figure 9 . typical supply current per output channel vs. data rate for 5 v and 3 v operation (no output load) 08340-017 current (ma) 0 1 2 3 4 0 5 10 15 20 25 30 d at a r a te (mbps) 5v 3v figure 10 . typical supply current per output channel vs. data r ate for 5 v and 3 v operation (15 pf output load) 08340-018 current (ma) 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 dat a r a te (mbps) 5v 3v figure 11 . typical adum7440 v dd1 supply current vs. data rate for 5 v and 3 v operation 08340-019 current (ma) 0 5 10 15 20 25 30 dat a r a te (mbps) 0 2 4 6 8 10 5v 3v figure 12 . typical adum7440 v dd2 supply current vs. data rat e for 5 v and 3 v operation 08340-020 current (ma) 0 5 10 15 20 25 30 dat a r a te (mbps) 5v 3v 0 5 10 15 20 25 30 35 figure 13 . typical adum7441 v dd1 supply current vs. data rate for 5 v and 3 v operation
adum7440/adum7441/adum7442 rev. b | page 13 of 20 08340-021 current (ma) 0 5 10 15 20 25 30 dat a r a te (mbps) 0 2 4 6 8 10 5v 3v figure 14 . typical adum7441 v dd2 supply current vs. data rate for 5 v and 3 v oper ation 08340-022 current (ma) 0 5 10 15 20 25 30 dat a r a te (mbps) 0 5 10 15 20 25 5v 3v figure 15 . typical adum7442 v dd1 or v dd2 supply current vs. data rate for 5 v and 3 v operation
adum7440/adum7441/a dum7442 rev. b | page 1 4 of 20 applications informa tion pc board layout the adum744x digital isolators require no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 16 ). a total of four bypass capacitors should be connected between pin 1 and pin 2 for v dd1a , bet ween pin 7 and pin 8 for v dd1b , between pin 9 and pin 10 for v dd2b , and between pin 15 and pin 16 for v dd2a . supply v dd1a pin 1 and v dd1b pin 7 should be connected together and supply v dd2b pin 10 and v dd2a pin 16 should be connected together. the capacito r values should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the power supply pin should not exceed 20 mm. v dd1a gnd 1 v ia v ib v ic/ v oc v id/ v od v dd1b gnd 1 v dd2a gnd 2 v oa v ob v oc/ v ic v od/ v id v dd2b gnd 2 08340-014 figure 16 . recommended printed circuit board layout in applications invol ving high common - mode transients, it is important to minimize board coupling across the isolation barrier. furthermore, users should design the board layout so that any coupling that does occur equally affects all pins on a given component side. failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch - up or permanent damage. propagation delay - related parameters propagation delay is a parameter that describes the ti me it takes a logic signal to propagate through a component. the input - to - output propagation delay time for a high - to - low transition may differ from the propagation delay time of a low - to - high transition. input (v ix ) output (v ox ) t plh t phl 50% 50% 08340-008 figure 17 . propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved. channel - to - channel matching refers to the maximum amount the prop agation delay differs between channels within a single adum744x component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum744x components operating under the same conditions. dc correctness and m agne tic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input lo gic transitions. in the absence of logic transitions at the input for more than ~1 s, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. if the decoder receives no internal pulses of mor e than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default high state by the watchdog timer circuit. the magnetic field immunity of the adum744x is determined by the ch anging magnetic field, which induces a voltage in the transformers receiving coil large enough to either falsely set or reset the decoder. the following analysis defines the conditions under which this can occur. the 3 v operating condition of the adum744 x is examined because it represents the most suscep - tible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced vo ltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ?d / dt ) r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). r n is the radius of the n th turn in the receiving coil (cm). n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum744x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. the result is shown in figure 18.
adum7440/adum7441/adum7442 rev. b | page 15 of 20 100 0 10 0 1 0 1 0 . 1 0 . 0 1 0 . 00 1 1 k 100 m 10 k maximum allowable magnetic flux (kgauss) 100 k 1 m 10 m m a g n e t i c f i e l d f r e q u e nc y ( h z) 08340-009 figure 18 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic fie ld of 0.5 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurred during a transmitted pulse (and was of the worst - case polari ty), it would reduce the received pulse from >1.0 v to 0.75 v, still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum744x transform ers. figure 19 shows these allowable current magnitudes as a function of frequency for selected distances. as shown, the adum744x is extremely immune and can be affected only by extremely large currents operated a t high frequency very close to the component. for the 1 mhz example noted previously, a 1.2 ka current would have to be placed 5 mm away from the adum744x to affect the operation of the component. 100 0 10 0 1 0 1 0 . 1 0 . 0 1 1 k 100 m 10 k maximum allowable current (ka) 100 k 1 m 10 m m a g n e t i c f i e l d f r e q u e nc y ( h z) d i s t anc e = 5m m d i s t anc e = 100m m d i s t anc e = 1 m 08340-010 figure 19 . maximum allowable cur rent for various current - to- adum744x spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce error voltages sufficiently large enough to trigger the thresholds of succeedi ng circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum744x isolator is a function of the supply voltage, the data rate of the channel, and the output l oad of the channel. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi (d) (2 f ? f r ) + i ddi ( q ) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0 .5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo ( q ) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz); it is half the input data rate, expressed in units of mbps. f r is the input stage refresh rate (mbps). i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma). to calculate the total v dd1 and v dd2 supp ly current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 8 and figure 9 show per - channel supply c urrents as a function of data rate for an unloaded output condition. figure 10 shows the per - channel supply current as a function of data rate for a 15 pf output condition. figure 11 through figure 15 show the total v dd1 and v dd2 supply current as a function of data rate for adum7440/ adum7441/adum7442 channel configurations. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulato ry agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the adum744x. analog devices performs accelerated life testing using voltage levels higher than the rated continuous workin g voltage. acceleration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 18 summarize the pea k voltage for 50 years of service life for a bipolar ac operating condition and the maximum csa approved working voltages. in many cases, the approved working voltage is higher than 50 - year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases.
adum7440/adum7441/a dum7442 rev. b | page 16 of 20 the insulation lifetime of the adum744x depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the wav eform is bipolar ac, unipolar ac, or dc. figure 20, figure 21 , and figure 22 illustrate these different isolation voltage w aveforms. bipolar ac voltage is the most stringent environment. the goal of a 50 - year operating lifetime under the ac bipolar condition determines the analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insu - lation is significantly lower. this allows operation at higher working voltages while still achieving a 50 - year service life. the working voltages listed in table 18 can be applied while maintaining t he 50 - year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. any cross - insulation voltage waveform that does not conform to figure 21 or figure 22 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50 - year lifetime voltage value listed in table 18. note that the voltage presented in figure 21 is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 08340-011 figure 20 . bipolar ac waveform 0v rated peak voltage 08340-012 figure 21 . unipolar ac waveform 0v rated peak voltage 08340-013 figure 22 . dc waveform
adum7440/adum7441/adum7442 rev. b | page 17 of 20 outline dimensions compli ant t o jedec st andard s mo-137-ab controlling dimens ions are in inches ; millim eter dimensions (in p arenth eses) are rounde d-off inch equiv alents for refere nce onl y and are not appropri a te for use in design . 16 9 8 1 s e a t i n g p l a n e 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 4 ( 0 . 1 0 ) 0 . 0 1 2 ( 0 . 3 0 ) 0 . 0 0 8 ( 0 . 2 0 ) 0 . 0 2 5 ( 0 . 6 4 ) b s c 0 . 0 4 1 ( 1 . 0 4 ) r e f 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 6 ( 0 . 1 5 ) 0 . 0 5 0 ( 1 . 2 7 ) 0 . 0 1 6 ( 0 . 4 1 ) 0 . 0 2 0 ( 0 . 5 1 ) 0 . 0 1 0 ( 0 . 2 5 ) 8 0 coplan arity 0.004 (0.10 ) 0 . 0 6 5 ( 1 . 6 5 ) 0 . 0 4 9 ( 1 . 2 5 ) 0 . 0 6 9 ( 1 . 7 5 ) 0 . 0 5 3 ( 1 . 3 5 ) 0 . 1 9 7 ( 5 . 0 0 ) 0 . 1 9 3 ( 4 . 9 0 ) 0 . 1 8 9 ( 4 . 8 0 ) 0 . 1 5 8 ( 4 . 0 1 ) 0 . 1 5 4 ( 3 . 9 1 ) 0 . 1 5 0 ( 3 . 8 1 ) 0 . 2 4 4 ( 6 . 2 0 ) 0 . 2 3 6 ( 5 . 9 9 ) 0 . 2 2 8 ( 5 . 7 9 ) 01- 28-2 008- a figure 23 . 16 - lead shrink sma ll outline package [qsop] (rq - 16) (dimensions shown in inches and (millimeters) ordering guide model 1 number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate maximum propagation delay, 5 v maximum pulse width distortion (ns) tempe rature range package description package option adum7440arqz 4 0 1 mbps 75 ns 25 ?40c to +105c 16 - lead qsop rq - 16 adum7440arqz - rl7 4 0 1 mbps 75 ns 25 ?40c to +105c 16 - l e a d q s o p, 7 tape and reel rq - 16 adum7440crqz 4 0 25 mbps 5 0 ns 5 ?40c to +105c 16 - lead qsop rq - 16 adum7440crqz - rl7 4 0 25 mbps 5 0 ns 5 ?40c to +105c 16 - lea d q s o p, 7 tape and reel rq - 16 adum7441arqz 3 1 1 mbps 75 ns 25 ?40c to +105c 16 - lead qsop rq - 16 adum7441arqz - rl7 3 1 1 mbps 75 ns 25 ?40c to +105c 16 - l e a d q s o p, 7 tape and reel rq - 16 adum7441crqz 3 1 25 mbps 5 0 ns 5 ?40c to +105c 16 - lead qsop rq - 16 adum7441crqz - rl7 3 1 25 mbps 5 0 ns 5 ?40c to +105c 16 - l e a d q s o p, 7 tape and reel rq - 16 adum7442arqz 2 2 1 mbps 75 ns 25 ?40c to +105c 16 - lead qsop rq - 16 adum7442arqz - rl7 2 2 1 mbps 75 ns 25 ?40c to +105c 16 - l e a d q s o p, 7 tape and reel rq - 16 adum7442crqz 2 2 25 mbps 5 0 ns 5 ?40c to +105c 16 - lead qsop rq - 16 adum7442crqz - rl7 2 2 25 mbps 5 0 ns 5 ?40c to +105c 16 - l e a d q s o p, 7 tape and reel rq - 16 1 z = rohs compliant part.
adum7440/adum7441/adum7442 rev. b | page 18 of 20 notes
adum7440/adum7441/adum7442 rev. b | page 19 of 20 notes
adum7440/adum7441/adum7442 rev. b | page 20 of 20 notes ? 2009 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08340 - 0- 2/11(b)

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